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| MM74HCT245 Octal 3-STATE Transceiver February 1984 Revised February 1999 MM74HCT245 Octal 3-STATE Transceiver General Description The MM74HCT245 3-STATE bi-directional buffer utilizes advanced silicon-gate CMOS technology and is intended for two-way asynchronous communication between data buses. It has high drive current outputs which enable high speed operation even when driving large bus capacitances. This circuit possesses the low power consumption of CMOS circuitry, yet has speeds comparable to low power Schottky TTL circuits. This device is TTL input compatible and can drive up to 15 LS-TTL loads, and all inputs are protected from damage due to static discharge by diodes to VCC and ground. The MM74HCT245 has one active low enable input (G), and a direction control (DIR). When the DIR input is HIGH, data flows from the A inputs to the B outputs. When DIR is LOW, data flows from B to A. MM74HCT devices are intended to interface between TTL and NMOS components and standard CMOS devices. These parts are also plug-in replacements for LS-TTL devices and can be used to reduce power consumption in existing designs. Features s TTL input compatible s 3-STATE outputs for connection to system busses s High output drive current: 6 mA (min) s High speed: 16 ns typical propagation delay s Low power: 80 A (74HCT Series) Ordering Code: Order Number MM74HCT245WM MM74HCT245SJ MM74HCT245MTC MM74HCT245N Package Number M20B M20D MTC20 N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code. Connection Diagram Pin Assignments for DIP, SOIC, SOP and TSSOP Truth Table Control Inputs G L L H H = HIGH Level L = LOW Level X = Irrelevant Operation DIR L H X 245 B data to A bus A data to B bus isolation Top View (c) 1999 Fairchild Semiconductor Corporation DS005366.prf www.fairchildsemi.com MM74HCT245 Logic Diagram www.fairchildsemi.com 2 MM74HCT245 Absolute Maximum Ratings(Note 1) (Note 2) Supply Voltage (VCC) DC Input Voltage (VIN) DC Output Voltage (VOUT) Clamp Diode Current (IIK, IOK) DC Output Current, DC VCC or GND Current, per pin (ICC) Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) S.O. Package only Lead Temperature (TL) (Soldering 10 seconds) 260C 600 mW 500 mW -0.5 to +7.0V -1.5 to VCC +1.5V -0.5 to VCC +0.5V 20 mA 35 mA 70 mA -65C to +150C Recommended Operating Conditions Min Supply Voltage (VCC) DC Input or Output Voltage (VIN, VOUT) Operating Temperature Range (TA) Input Rise or Fall Times (tr, tf) 500 ns Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating -- plastic "N" package: - 12 mW/C from 65C to 85C. Max 5.5 VCC +85 Units V V C 4.5 0 -40 DC Electrical Characteristics (VCC = 5V 10%, unless otherwise specified.) Symbol VIH VIL VOH Parameter Minimum HIGH Level Input Voltage Maximum LOW Level Input Voltage Minimum HIGH Level Output Voltage VIN = VIH or VIL |IOUT | = 20 A |IOUT | = 6.0 mA, VCC = 4.5V |IOUT | = 7.2 mA, VCC = 5.5V VOL Maximum LOW Level Voltage VIN = VIH or VIL |IOUT | = 20 A |IOUT | = 6.0 mA, VCC = 4.5V |IOUT | = 7.2 mA, VCC = 5.5V IIN IOZ Maximum Input Current Maximum 3-STATE Output Leakage Current ICC Maximum Quiescent Supply Current VIN = VCC or GND IOUT = 0 A VIN = 2.4V or 0.5V (Note 4) Note 4: Measured per input. All other inputs at VCC or ground. Conditions TA = 25C Typ 2.0 0.8 TA = -40 to 85C TA = -55 to 125C Guaranteed Limits 2.0 0.8 2.0 0.8 Units V V VCC 4.2 5.2 0 0.2 0.2 VCC- 0.1 3.98 4.98 0.1 0.26 0.26 0.1 0.5 VCC- 0.1 3.84 4.84 0.1 0.33 0.33 1.0 5.0 VCC- 0.1 3.7 4.7 0.1 0.4 0.4 1.0 10 V V V V V V A A VIN = VCC or GND, VIH or VIL, Pin 1 or 19 VOUT = VCC or GND G = VIH 8 0.6 1.0 80 1.3 160 1.5 A mA 3 www.fairchildsemi.com MM74HCT245 AC Electrical Characteristics VCC = 5.0V, tr = tf = 6 ns, TA = 25C (unless otherwise specified) Symbol tPHL, tPLH tPZL, tPZH tPLZ, tPHZ Parameter Maximum Output Propagation Delay Maximum Output Enable Time Maximum Output Disable Time CL = 45 pF RL = 1 k CL = 5 pF RL = 1 k 20 25 ns 29 40 ns CL = 45 pF Conditions Typ 16 Guaranteed Limit 20 Units ns AC Electrical Characteristics VCC = 5.0V 10%, tr = tf = 6 ns (unless otherwise specified) Symbol tPHL, tPLH tPZL tPZH tPHZ, tPLZ tTHL, tTLH CIN COUT CPD Parameter Maximum Output Propagation Delay Maximum Output Enable Time Maximum Output Enable Time Maximum Output Disable Time Maximum Output Rise and Fall Time Maximum Input Capacitance Maximum Output/Input Capacitance Power Dissipation Capacitance G = VCC (Note 5) G = GND 7 100 pF pF 20 25 25 25 pF 10 15 15 15 pF Conditions CL = 50 pF CL = 150 pF RL = 1 k CL = 50 pF RL = 1 k CL = 50 pF RL = 1 k CL = 50 pF CL = 50 pF 8 12 15 18 ns 21 30 38 45 ns 23 33 41 49 ns TA = 25C Typ 17 24 31 23 30 42 TA = -40 to 85C TA= -55 to 125C Guaranteed Limits 29 38 53 34 45 63 ns ns ns Units Note 5: CPD determines the no load power consumption, PD = CPD VCC2 f + I CCVCC, and the no load dynamic current consumption, IS = CPD V CC f + ICC. www.fairchildsemi.com 4 MM74HCT245 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D 5 www.fairchildsemi.com MM74HCT245 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 www.fairchildsemi.com 6 MM74HCT245 Octal 3-STATE Transceiver Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N20A LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. |
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